A Study Of Relaxation Techniques For The Transient Analysis Of Digital Circuits

In the VLSI microelectronics era, the cost of the immense CPU time and memory storage for a 'standard' circuit simulator has become prohibitive. In order to achieve dramatic improvement in the performance of the circuit simulator, there are two principal points of departure from the 'standard' simulation approach, namely, 'tearing' decomposition and 'relaxation' decomposition. This research is to study the numerical convergence and stability properties of several of the relaxation algorithms that have been proposed for the simulation of VLSI circuits. The time-point Gauss-Seidel method with prediction, the exploitation of latency and event scheduling algorithms are implemented into a general purpose circuit simulator SLATE-R (a Simulator with Latency and Tearing --Relaxed version). The performance of the SLATE-R program in the analysis of various types of integrated circuit technologies is studied. Keywords include: Microelectronics, standard, tearing, relaxation, decomposition, and exploitation.