Analytical And Experimental Investigation Of Thermal Transport In Three Dimensional Integrated Circuits 3d Ics

Thermal management of three-dimensional integrated circuits (3D ICs) is recognized to be one of the foremost technological and research challenges currently blocking the widespread adoption of this promising technology. The computation of steady-state temperature fields in a 3D IC is critical for determining the thermal characteristics of a 3D IC and for evaluating any candidate thermal management technology. An analytical solution for the three-dimensional temperature field in a 3D IC based on solution of the governing energy equations using Fourier series expansion for steady-state temperature fields is studied. Comparison of the predicted temperature fields with finite-element simulation shows excellent agreement. The model is used to compute the temperature field in a 3D IC, and it is shown that by utilizing a thermalfriendly floorplanning approach, the maximum temperature of the 3D IC is reduced significantly. Several 3D IC manufacturing and packaging approaches require adjacent die sizes to be different from one another since this enables differentiated manufacturing and design. However, it is expected that unequally-sized die may cause deteriorated thermal performance due to heat spreading and constriction. Heat transfer model for predicting the three-dimensional temperature field in a multi-die 3D IC with unequally-sized die is studied. The model is used to compare the thermal performance of unequally-sized die stacks with a uniformly-sized die stack. Results indicate that the greater the degree of non-uniformity in the die stack, the greater in the peak temperature rise. An analytical modeling of heat transfer in interposer-based microelectronic systems is described. The analytical model is developed to study the effect of various parameters on the temperature field in an interposer system. A non-iterative, analytical heat transfer model for computing three-dimensional temperature fields in a 3D IC has been proposed. The governing energy equations with appropriate boundary conditions for N-die stack with different values of N are solved by first writing the solution in terms of infinite series, followed by deriving and solving ordinary differential equations for the coefficients in the series. Steady-state temperature fields predicted by the model compare well with FEM-based simulation results and previously developed iterative models. In addition, temperature computation based on the proposed models is much faster than numerical simulations or iterative approach. Expressions for the temperature field are derived for perfect contact between layers as well as for non-zero thermal resistance between layers. Several applications of the model are also discussed. These include temperature computation for a 3D IC with a large number of strata, as well as the effect of inter-die thermal contact resistance. The results may find applications in development of tools for rapid thermal computation for 3D ICs. Experimental measurements help validate thermal models for predicting the temperature field in a 3D IC. Experimental results on thermal performance of a two-die 3D IC are presented. Heaters and temperature sensor circuits embedded in each layer are utilized to generate heat and measure temperature rise in each layer respectively. Both steadystate and transient data are reported. The experimental setup and theoretical model for measuring thermal contact resistance between two adjacent die introduced and the experimental value of thermal contact resistance compere well with theoretical model result. The experimental setup and procedure are described and the results used to determine inter-die thermal resistance of two-die stack.