Trace-Based Post-Silicon Validation for VLSI Circuits

Trace-Based Post-Silicon Validation for VLSI Circuits
Author: Xiao Liu
Publisher: Springer Science & Business Media
Total Pages: 118
Release: 2013-06-12
Genre: Technology & Engineering
ISBN: 3319005332

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This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits. The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective. A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuits, and ultimately enable the design and fabrication of reliable electronic devices.


Trace-Based Post-Silicon Validation for VLSI Circuits
Language: en
Pages: 118
Authors: Xiao Liu
Categories: Technology & Engineering
Type: BOOK - Published: 2013-06-12 - Publisher: Springer Science & Business Media

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This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLS
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This book provides a comprehensive coverage of System-on-Chip (SoC) post-silicon validation and debug challenges and state-of-the-art solutions with contributio
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Type: BOOK - Published: 2013 - Publisher:

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Pre-silicon verification is an essential part of integrated circuit design to capture functional design errors. Complex simulation, emulation and formal verific
Network-on-Chip Security and Privacy
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This book provides comprehensive coverage of Network-on-Chip (NoC) security vulnerabilities and state-of-the-art countermeasures, with contributions from System
VLSI Design and Test
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Authors: Brajesh Kumar Kaushik
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This book constitutes the refereed proceedings of the 21st International Symposium on VLSI Design and Test, VDAT 2017, held in Roorkee, India, in June/July 2017