Multimodal Implantable Neural Interfacing Microsystem

Studying brain functionality to help patients suffering from neurological diseases needs fully implantable brain interface to enable access to neural activities as well as read and analyze them. In this thesis, ultra-low power implantable brain-machine-interfaces (BMIs) that are based on several innovations on circuits and systems are studied for use in neural recording applications. Such a system is intended to collect information on neural activity emitted by several hundreds of neurons, while activating them on demand using actuating means like electro- and/or photo-stimulation. Such a system must provide several recording channels, while consuming very low energy, and have an extremely small size for safety and biocompatibility. Typically, a brain interfacing microsystem includes several building blocks, such as an analog front-end (AFE), an analog-to-digital converter (ADC), digital signal processing modules, and a wireless data transceiver. A BMI extracts neural signals from noise, digitizes them, and transmits them to a base station without interfering with the natural behavior of the subject. This thesis focuses on ultra-low power front-ends to be utilized in a BMI, and presents front-ends with several innovative strategies to consume less power, while enabling high-resolution and high-quality of data. First, we present a new front-end structure using a current-reuse scheme. This structure is scalable to huge numbers of recording channels, owing to its small implementation silicon area and its low power consumption. The proposed current-reuse AFE, which includes a low-noise amplifier (LNA) and a programmable gain amplifier (PGA), employs a new fully differential current-mirror topology using fewer transistors. This is an improvement over several design parameters, in terms of power consumption and noise, over previous current-reuse amplifier circuit implementations. In the second part of this thesis, we propose a new multi-channel sigma-delta converter that converts several channels independently using a single op-amp and several charge storage capacitors. Compared to conventional techniques, this method applies a new interleaved multiplexing scheme, which does not need any reset phase for the integrator while it switches to a new channel; this enhances its resolution. When the chip area is not a priority, other approaches can be more attractive, and we propose a new power-efficient strategy based on a new in-channel ultra-low power sigma-delta converter designed to decrease further power consumption. This new converter uses a low-voltage architecture based on an innovative feed-forward topology that minimizes the nonlinearity associated with low-voltage supply.